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Physical Measurement Laboratory /Nanoscale Device Characterization Division

Alternative Computing Group

The Alternative Computing Group has two related programs addressing future electronics for information processing. Select an area below for more information​.

Hardware for Artificial Intelligence
Hardware for Artificial Intelligence
Nanotechnology Xccelerator
On-Silicon Metrology​

The Alternative Computing Group conducts wide ranging, cross-disciplinary research focusing on innovative measurement science in nanotechnology with an emphasis on applications in future electronics and information processing.   Our team consists of physicists and electrical engineers with a broad range of theoretical and experimental expertise. Core competencies include:​

  • Theoretical and experimental device physics research​

  • Emerging AI hardware and architectures ​

  • CMOS chip design​

  • Embedded systems for electronics instrumentation​

These capabilities combine in research programs that support development of new paradigms in nanoelectronics and computing by advancing measurement science in these areas. The group has programs in hardware for artificial intelligence and CMOS-based measurement platforms, exploring the measurement needs of chip-scale prototyping of novel-device-based technologies.

News and Updates

Projects and Programs

Microscope image of a crossbar array

Hardware Accelerators for Neural Networks

Ongoing
One promising candidate for building a hardware accelerator comes from the field of spintronics, where information is carried by electronic spin rather than charge. Magnetic tunnel junctions are particularly suited because of their multifunctionality and compatibility with standard integrated
Temporal Chip

Hardware Accelerators for Statistical Computing

Ongoing
Finding good solutions to many hard problems, like combinatorial optimization and traveling salesman problems, counterintuitively requires making the estimated solution worse before making it better. This situation results from many hard problems having many “solutions” that cannot be improved
Small array of transistors designed for single device integration.

Integrated CMOS Testbeds for Nanoelectronics and Machine Learning

Ongoing
The increasingly complex device requirements for next-generation computing architectures such as neuromorphic computing or nanoelectronic machine learning accelerators present challenges for researchers across the spectrum of institutions, from small businesses and universities to government
Crossbar Memory Arrays

Integrated Testbeds for Advanced Metrology

Ongoing
Crossbar Memory Arrays An especially prolific structure in memory architectures aimed at accelerating neural network operation is the crossbar array (Fig. 1). We produce medium-scale arrays that hold up to 20,000 nanodevices which can be characterized, read from, and written to individually or in

Publications

Strain-programmable van der Waals magnetic tunnel junctions

Author(s)
John Cenker, Dmitry Ovchinnikov, Harvey Yang, Daniel Chica, Catherine Zhu, Jiaqi Cai, Geoffrey Diederich, Zhaoyu Liu (刘曌玉), Xiaoyang Zhu, Xavier Roy, Ting Cao, Matthew Daniels, Jiun-Haw Chu, Di Xiao, Xiaodong Xu
Magnetic tunnel junctions (MTJs) are foundational spintronics devices with applications ranging from stable magnetic memory to emerging stochastic computing

Awards

2023 IEEE EDS Leo Esaki Award

2023 IEEE EDS Leo Esaki Award

For recognizing the best paper appearing in a fast turnaround archival publication of the IEEE Electron Devices Society, targeted to the

Press Coverage

A dense grid of purple, blue and red lines on a square platform.

NIST, Google announce chip R&D partnership

FCW
The National Institute of Standards and Technology entered into a new agreement with search engine behemoth Google to help manufacture more chip technology that

Contacts

Group Leader

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